
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 28: IO_FIFO Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
IO_FIFO Clock to Out Delays
T OFFCKO_DO
T CKO_FLAGS
RDCLK to Q outputs
Clock to IO_FIFO Flags
0.51
0.59
0.56
0.62
0.63
0.81
0.63
0.81
0.81
0.77
ns
ns
Setup/Hold
T CCK_D /T CKC_D
D inputs to WRCLK
0.43/–0.01 0.47/–0.01 0.53/–0.01
0.53/0.09
0.76/–0.05
ns
T IFFCCK_WREN /T IFFCKC_WREN
WREN to WRCLK
0.39/–0.01 0.43/–0.01 0.50/–0.01 0.50/–0.01 0.70/–0.05
ns
T OFFCCK_RDEN /T OFFCKC_RDEN
RDEN to RDCLK
0.49/0.01
0.53/0.02
0.61/0.02
0.61/0.02
0.79/–0.02
ns
Minimum Pulse Width
T PWH_IO_FIFO
T PWL_IO_FIFO
RESET, RDCLK, WRCLK
RESET, RDCLK, WRCLK
0.81
0.81
0.92
0.92
1.08
1.08
1.08
1.08
1.29
1.29
ns
ns
Maximum Frequency
F MAX
RDCLK and WRCLK
533.05
470.37
400.00
400.00
333.33
MHz
DS182 (v2.8) March 4, 2014
Product Specification
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